The present invention relates to a semiconductor device; and, more particularly, to a semiconductor device having a capacitor structure for use in a memory cell and a method for the manufacture thereof.
As is well known, a dynamic random access memory (DRAM) with a memory cell comprised of a transistor and a capacitor has a higher degree of integration mainly by down-sizing through micronization. However, there is still a demand for downsizing the area of the memory cell.
To meet this demand, several methods have been proposed, such as a trench type or a stack type capacitor, which is arranged three-dimensionally in a memory device to reduce the cell area available to the capacitor. However, the process of manufacturing a three-dimensionally arranged capacitor is a long and tedious one and consequently incurs high manufacturing costs. Therefore, there is a strong demand for a new memory device that can reduce the cell area while securing a requisite volume of information without requiring complex manufacturing steps.
DRAM devices employ a high dielectric material as a capacitor thin film, such as barium strontium titanate (BST) and tantalum oxide (Ta2O5), to meet the demand. While DRAM is small, inexpensive, fast, and expends little power, DRAM memory has problems in that it is volatile and has to be refreshed many times each second.
In an attempt to solve the above problem of DRAM, there have been proposed a ferroelectric random access memory (FeRAM) where a capacitor thin film with ferroelectric properties such as strontium bismuth tantalate (SBT) and lead zirconate titanate (PZT) is used for a capacitor in place of a conventional silicon oxide film or a silicon nitride film. FeRAM has a non-volatile property due to remnant polarization of a ferroelectric material and it can operate at lower voltages.
In manufacturing a memory device such as DRAM and FeRAM, there is a step of forming a passivation layer on top of a metal interconnection layer, for protecting the semiconductor device from exposure to detrimental environmental factors such as moisture, particles or the like. The passivation layer is formed by using a method such as plasma enhanced chemical vapor deposition (PECVD) in hydrogen rich ambient. However, during the passivation process, the hydrogen gas generated by the PECVD process degrades the capacitor of the memory cell. That is, the hydrogen gas and ions penetrate to a top electrode and a side of the capacitor, reaching to the capacitor thin film and reacting with oxygen atoms constituting the ferroelectric material of the capacitor thin film. These problems, therefore, tend to make it difficult to obtain the desired reproducibility, reliability and yield in fabricating the memory cell.
It is, therefore, an object of the present invention to provide a semiconductor device incorporating therein a double hydrogen barrier layer provided with a titanium (Ti) layer and a tetra-ethyl-ortho-silicate (TEOS) oxide layer to protect a capacitor from hydrogen damage after forming a metal interconnection.
It is another object of the present invention to provide a method for manufacturing a semiconductor device incorporating the double hydrogen barrier layer therein to protect a capacitor from hydrogen damage during the formation of a passivation layer.
In accordance with one aspect of the present invention, there is provided a semiconductor device for use in a memory cell, including: an active matrix provided with a transistor and a first insulating layer formed around the transistor; a capacitor structure, formed on top of the first insulating layer, composed of a bottom electrode, a capacitor thin film placed on top of the bottom electrode and a top electrode formed on top of the capacitor thin film; a second insulating layer formed on top of the transistor and the capacitor structure; a metal interconnection formed on top of the second insulating layer and the active matrix to electrically connect the transistor to the capacitor structure; and a hydrogen barrier layer formed on top of the metal interconnection.
In accordance with another aspect of the present invention, there is provided a method for manufacturing a semiconductor device for use in a memory cell, the method comprising steps of: a) preparing an active matrix provided with a transistor and a first insulating layer formed around the transistor; b) forming a capacitor structure on top of the first insulating layer, with the capacitor structure including a capacitor thin film made of a ferroelectric material; c) forming a second insulating layer on top of the capacitor and transistor structure; d) forming a metal interconnection layer and patterning the metal interconnection into a predetermined configuration to electrically connect the transistor to the capacitor structure; and e) forming a hydrogen barrier layer on top of the metal interconnection.